The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Dec. 22, 2022
Applicant:

Mediatek Inc., Hsinchu City, TW;

Inventors:

Shih-Yi Syu, Hsinchu City, TW;

Wen-Chou Wu, Hsinchu City, TW;

Assignee:

MEDIATEK INC., Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01); H10W 90/24 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 70/611 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/114 (2026.01); H10W 90/401 (2026.01); H10W 90/701 (2026.01); H10W 90/24 (2026.01); H10W 90/722 (2026.01); H10W 90/754 (2026.01);
Abstract

A semiconductor package assembly is provided. The semiconductor package assembly includes a fan-out package and a memory package stacked on the fan-out package. The fan-out package includes a first redistribution layer (RDL) structure, a first logic die, through via (TV) interconnects, and first conductive structures. The first logic die and the first conductive structures are in contact with the first RDL structure. The TV interconnects are electrically connected to the first RDL structure. The memory package includes a first substrate, a memory die, and second conductive structures. The memory die and the second conductive structures are disposed on the first substrate. The memory die is electrically connected to the first logic die using the TV interconnects and the first RDL structure. The semiconductor package assembly further includes a second substrate electrically connected to the first logic die using the first conductive structures.


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Syu, Shih-Yi. (2026). Semiconductor package assembly (U.S. Patent No. 12787868). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12787868

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