The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Sep. 28, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jinyoung Kim, Suwon-si, KR;

Wonbin Shin, Suwon-si, KR;

Kiseok Kim, Suwon-si, KR;

Jihye Shim, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 74/10 (2026.01); H10B 80/00 (2026.01); H10W 70/60 (2026.01); H10W 70/685 (2026.01); H10W 72/00 (2026.01); H10W 72/30 (2026.01); H10W 72/90 (2026.01); H10W 74/47 (2026.01); H10W 80/00 (2026.01); H10W 90/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 74/121 (2026.01); H10B 80/00 (2023.02); H10W 70/685 (2026.01); H10W 74/476 (2026.01); H10W 90/00 (2026.01); H10W 90/701 (2026.01); H10W 70/60 (2026.01); H10W 72/0198 (2026.01); H10W 72/354 (2026.01); H10W 72/823 (2026.01); H10W 72/9415 (2026.01); H10W 80/312 (2026.01); H10W 80/327 (2026.01); H10W 80/743 (2026.01); H10W 90/297 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01); H10W 90/792 (2026.01); H10W 90/794 (2026.01);
Abstract

A semiconductor package includes a first chip including a first substrate, a first wiring layer on the first substrate, and a plurality of through-electrodes to be connected to the first wiring layer and protruding from a lower surface of the first substrate, a double gap-fill layer covering a side surface and a lower surface of the first chip and a protruding portion of the through-electrode and having a double layer structure, a second chip disposed on the first chip and the double gap-fill layer, including a second wiring layer and a second substrate on the second wiring layer, and bonded to the first chip by hybrid bonding, and a bump on a lower surface of the first chip and connected to the through-electrode.


Find Patent Forward Citations

Quick Actions:

Kim, Jinyoung. (2026). Semiconductor package and method for manufacturing the same (U.S. Patent No. 12787852). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12787852

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