The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Mar. 17, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Minho Lee, Cheonan-si, KR;

Jaewook Yoo, Asan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 46/00 (2026.01); B81C 99/00 (2010.01); H10P 72/50 (2026.01); H10W 70/05 (2026.01); H10W 70/09 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 70/655 (2026.01); H10W 70/68 (2026.01); H10W 70/685 (2026.01); H10W 70/695 (2026.01); H10W 72/00 (2026.01); H10W 72/90 (2026.01); H10W 74/10 (2026.01); H10W 80/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 46/607 (2026.01); B81C 99/007 (2013.01); H10P 72/53 (2026.01); H10W 46/00 (2026.01); H10W 46/301 (2026.01); H10W 46/603 (2026.01); H10W 70/05 (2026.01); H10W 70/09 (2026.01); H10W 70/65 (2026.01); H10W 70/655 (2026.01); H10W 70/68 (2026.01); H10W 70/682 (2026.01); H10W 70/685 (2026.01); H10W 70/695 (2026.01); H10W 72/985 (2026.01); H10W 74/117 (2026.01); H10W 80/163 (2026.01); H10W 90/00 (2026.01); H10W 90/701 (2026.01); H10W 90/724 (2026.01); H10W 90/7295 (2026.01); H10W 90/734 (2026.01); H10W 90/754 (2026.01); H10W 46/101 (2026.01); H10W 70/60 (2026.01); H10W 72/07178 (2026.01); H10W 90/722 (2026.01);
Abstract

Provided are package-on-package (POP)-type semiconductor packages including a lower package having a first size and including a lower package substrate in which a lower semiconductor chip is, an upper redistribution structure on the lower package substrate and the lower semiconductor chip, and alignment marks. The packages may also include an upper package having a second size smaller than the first size and including an upper package substrate and an upper semiconductor chip. The upper package substrate may be mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and the upper semiconductor chip may be on the upper package substrate. The alignment marks may be used for identifying the upper package, and the alignment marks may be below and near outer boundaries of the upper package on the lower package.


Find Patent Forward Citations

Quick Actions:

Lee, Minho. (2026). Package-on-package (pop) type semiconductor packages (U.S. Patent No. 12787796). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12787796

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