Charge transfer device having a taper at the gate for clock frequencies from 100 mhz

Abstract

A charge transfer device having a charge transfer channel in a semiconductor substrate. A doped conduction layer is provided for movably accepting the charge carriers, and a sequence of at least two electrically isolated gates which adjacently succeed one another for transferring the charge carriers in the conduction layer in a flow direction is provided. The charge transfer channel is formed by overlap of the possible electrostatic effect of the gates with the conduction layer. A clock generator has a clock frequency of more than 100 MHz which applies changes in potential at the clock frequency to the gates, for transporting charge carriers at the clock frequency from adjacent regions of the overlap between adjacent gates and the conduction layer. The charge transfer channel in the region of one gate has a region of a constriction in which the cross-section in the flow direction decreases, and has a region with a constant or widened cross-section.