The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Aug. 29, 2023
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Junichi Hashimoto, Yokkaichi Mie, JP;

Toshiyuki Sasaki, Yokkaichi Mie, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H10B 43/10 (2023.01); H10B 43/50 (2023.01); H10B 80/00 (2026.01); H10D 64/01 (2025.01); H10W 90/00 (2026.01); H10W 80/00 (2026.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H10B 80/00 (2023.02); H10W 90/00 (2026.01); H10W 80/312 (2026.01); H10W 80/327 (2026.01); H10W 90/792 (2026.01);
Abstract

According to one embodiment, a semiconductor memory device includes a lower layer, a stacked body above the lower layer with first conductive layers and first insulating layers alternately stacked. A pillar penetrates through the stacked body to reach the lower layer. At least one first insulating layer other than the lowest among the first insulating layers in a first region of the stacked body is thicker than first insulating layers in a second region above the first region. The pillar has a first bowing shape at the height of the at least one thicker first insulating layer and a second bowing shape at a height in the second region.


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Hashimoto, Junichi. (2026). Semiconductor memory device and manufacturing method of semiconductor memory device (U.S. Patent No. 12787283). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12787283

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