Time-domain analog-to-digital converter

Abstract

An ADC () is disclosed. It has two VTCs () for converting a first and a second input voltage, respectively, to pulses with delays corresponding to the magnitudes of these voltages. It further has a pulse-detector circuit () coupled to outputs () of the two VTCs (). The pulse-detector circuit () is configured to make a transition from a first logic state ('0') to a second logic state (‘F) at a first output () of the pulse-detector circuit () in response to the start of the pulse from one of the VTCs () and to make a transition from the first logic state (‘0’) to the second logic state (‘F) at a second output () of the pulse-detector circuit () in response to the start of the pulse from the other VTC. Furthermore, the pulse-detector circuit () is configured to reset both the first and the second output () to the first logic state (‘0’) in response to both the first output () and the second output () of the pulse-detector circuit () being set in the second logic state (‘1’). The ADC () further has a first TDC () coupled to the first output () of the pulse-detector circuit () and a second TDC () coupled to the second output () of the pulse-detector circuit ().