The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Jan. 07, 2025
Applicant:

Cxmt Corporation, Hefei City, CN;

Inventors:

Jiapeng Zhang, Hefei City, CN;

Yoonjoo Eom, Hefei City, CN;

Jaehun Jung, Hefei City, CN;

Assignee:

CXMT Corporation, Hefei City, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/081 (2006.01); G11C 11/4076 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0818 (2013.01); G11C 11/4076 (2013.01);
Abstract

A delay measurement circuit includes: a loop flag generation circuit configured to: generate a loop flag signal and input the loop flag signal to the loop of the delay-locked loop when loop delay measurement is performed on the delay-locked loop; and generate a measurement finish signal and generate a target pulse signal after the loop flag signal is cycled for M times in the loop of the delay-locked loop, a valid pulse width of the target pulse signal being equal to M times a loop delay; and a counter circuit configured to: receive a divided clock signal; time the valid pulse width of the target pulse signal based on the divided clock signal, to obtain a timing result; and perform preset processing on the timing result, to obtain a loop delay measurement result of the delay-locked loop.


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Zhang, Jiapeng. (2026). Delay measurement circuit and memory (U.S. Patent No. 12785697). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12785697

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