The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Oct. 26, 2023
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventor:

Ji Hyo Kang, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/017 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
H03K 19/01742 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01);
Abstract

A buffer circuit includes a driving control circuit and a driving circuit. The driving control circuit changes a voltage level of an input signal to generate a pull-up control signal and a pull-down control signal. The pull-up control signal has a voltage level lower than a high boundary voltage level of the input signal. The pull-down control signal has a voltage level higher than a low boundary voltage level of the input signal. The driving circuit generates an output signal based on the pull-up control signal and the pull-down control signal.


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Kang, Ji. (2026). Buffer circuit, clock generating circuit, semiconductor apparatus and semiconductor system using the same (U.S. Patent No. 12785690). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12785690

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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