The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2026
Filed:
Mar. 20, 2024
Applicant:
Advanced Micro Devices, Inc., Santa Clara, CA (US);
Inventor:
Russell Schreiber, Austin, TX (US);
Assignee:
Advanced Micro Devices, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/52 (2006.01); G11C 29/00 (2006.01); H10D 88/00 (2025.01); H10W 20/20 (2026.01);
U.S. Cl.
CPC ...
G11C 29/52 (2013.01); G11C 29/802 (2013.01); H10D 88/00 (2025.01); H10W 20/20 (2026.01);
Abstract
Systems and devices for signal redundancy in stacked chip architectures can include an integrated circuit that incorporates a voting circuit. The voting circuit can be configured to receive multiple redundant copies of a signal input and remedy faults in a transmission pathway of the signal input by producing a signal output that reflects a majority among received versions of the signal input.
Quick Actions:
Schreiber, Russell. (2026). Apparatuses, systems, and methods for signal redundancy in stacked-chip architectures (U.S. Patent No. 12784865). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12784865
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile