The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

May. 18, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventor:

Kok Wah Khor, Nibong Tebal, MY;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/12 (2006.01); G11C 29/18 (2006.01);
U.S. Cl.
CPC ...
G11C 29/12 (2013.01); G11C 29/18 (2013.01);
Abstract

An integrated circuit includes sectors of logic circuits. Each of the sectors of logic circuits includes a local sector manager controller circuit that provides an indication to perform a memory test. Each of the sectors also includes a built-in-self-test circuit that is configurable to generate a control signal and expected data in response to the indication to perform the memory test. Each of the sectors also includes a memory circuit that outputs read data in response to the control signal during the memory test. Each of the sectors further includes a comparator circuit configurable to compare the read data with the expected data during the memory test to generate a test result that is provided to the built-in-self-test circuit.


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Khor, Kok. (2026). Built-in-self-test circuits and methods in sectors of integrated circuits (U.S. Patent No. 12784856). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12784856

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