Memory device changing clock frequency according to the number of active blocks and storage device including the same

Abstract

A memory device is disclosed including a memory cell array, a voltage generator, and a control logic. The memory cell array has a plurality of active blocks, each active block including a plurality of memory cells operating at the same clock frequency. The voltage generator provides an operating voltage to the plurality of memory cells. The control logic controls an independent memory operation for each active block. The voltage generator includes a pump circuit which changes a clock frequency for generating the operating voltage according to a number of active blocks activated during the independent memory operation.