The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Feb. 11, 2025
Applicant:

Nuvoton Technology Corporation Japan, Kyoto, JP;

Inventor:

Atsushi Mototani, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 5/06 (2006.01); G11C 7/04 (2006.01); G11C 8/08 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 11/418 (2013.01); G11C 5/063 (2013.01); G11C 7/04 (2013.01); G11C 8/08 (2013.01); G11C 11/419 (2013.01);
Abstract

A semiconductor memory device includes: a first pull-down n-channel MOS transistor that includes: a drain connected to a word line; a source connected to a ground line; and a gate connected to a first node; a first series connection n-channel MOS transistor that includes: a drain connected to a power supply line; and a source connected to the first node; and a second series connection n-channel MOS transistor that includes: a drain connected to the first node; and a source connected to the ground line. The inverse-logic signal of a signal to be input to the gate of the second series connection n-channel MOS transistor is input to the gate of the first series connection n-channel MOS transistor.


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Mototani, Atsushi. (2026). Semiconductor memory device (U.S. Patent No. 12784819). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12784819

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