Sense amplifier circuit having bitline sense amplifers and equalizing circuit and semiconductor memory device including the same

Abstract

A sense amplifier circuit including bitline sense amplifiers each of which includes an amplifying circuit, an isolation circuit, an offset cancellation circuit, and an equalizer circuit. The amplifying circuit is connected to a bitline and a complementary bitline to adjust a voltage of a sensing bitline and a complementary sensing bitline. The isolation circuit connects the bitline and the complementary bitline to the complementary sensing bitline and the sensing bitline. The offset cancellation circuit connects the bitline and the complementary bitline to the sensing bitline and the complementary sensing bitline. The equalizer circuit equalizes the bitline and the complementary bitline to a precharge voltage, and includes an equalizing transistor. An active region is formed such that sources of equalizing transistors of first and second bitline sense amplifiers are connected and sources of equalizing transistors of first and third bitline sense amplifiers are separated.