Bit-line sense amplifier and semiconductor memory device including the same

Abstract

A semiconductor memory device includes a bit-line sense amplifier that includes an amplifying circuit connected to a bit-line, a complementary bit-line, a sensing bit-line, a complementary sensing bit-line, an offset cancellation circuit, an equalizer and an isolation circuit. The offset cancellation circuit connects the bit-line and the complementary bit-line to the complementary sensing bit-line and the sensing bit-line, respectively, based on an offset cancellation signal. The equalizer provides a precharge voltage to the sensing bit-line and the complementary sensing bit-line based on an equalizing signal. The isolation circuit is connected between the bit-line and the sensing bit-line and between the complementary bit-line and the complementary sensing bit-line, and connects the sensing bit-line and the complementary sensing bit-line equalized with the precharge voltage to the bit-line and the complementary bit-line, respectively, based on an isolation signal.