Memory controller performing training and operation method thereof

Abstract

The memory controller includes a multi-phase clock generator generating first to N-th clocks having N different phases, a write clock generator generating monitoring signals having a logic state corresponding to bits of the data pattern, a duty adjuster adjusting duties of the first to N-th clocks, a skew adjuster adjusting a skew of at least one of the first to N-th clocks, and a training circuit controlling a training operation for adjusting the duties and skews of the first to N-th clocks, wherein, during a first training process of adjusting the duties of the first to N-th clocks, first to N-th monitoring signals having waveforms corresponding to the first to N-th clocks are generated using data patterns having different values, and the duty of each of the first to N-th clocks is adjusted based on a result of monitoring each of duties of the first to N-th monitoring signals.