Wiring pattern-based parasitic capacitance extraction

Abstract

A target wire is separated into one set of segments based on effective spaces of crossing wires at one target-wire side, and another set of segments based on effective spaces of crossing wires at another target-wire side. Effective widths of crossing wires at the one and other target-wire sides are accumulated. One effective length factor for crossing wires at the one target-wire side is determined, and another effective length factor for crossing wires at the other target-wire side is determined. One or more capacitance values are ascertained for the one and other target-wire sides with reference to a data structure of capacitance per-unit-length for identified configurations. A total capacitance is determined using the effective length factors, and the ascertained capacitance values. An impact of the determined total capacitance on circuit performance is assessed, and based on the assessing, the wiring pattern of the integrated circuit is modified.