Network devices with multi-interface bridge and count aggregation and publishing circuitry

Abstract

A network device can include a main processor and a packet processor. The packet processor can include multiple physical interfaces operable to communicate with external processors using different communications protocols, data storage elements, and a multi-interface bridge that enables the external processors to access the data storage elements using a common address map. The packet processor can include multiple input-output ports, host interface counter circuitry coupled to an external processor via one or more register interfaces, and client interface counter circuitry configured to accumulate count values for at least some of the input-output ports and to write the accumulated count values into memory on the host interface counter circuitry. The accumulated count values can be published by the host interface counter circuitry to a local or remote server via a statistics publishing interface.