Chip, terminal, floating-point operation control method, and related apparatus

Abstract

A floating-point operation control method, applied to a chip comprising a multiply accumulator, includes receiving a first selection signal, and controlling an operation circuit in the multiply accumulator corresponding to a floating-point operation mode indicated by the first selection signal. The floating-point operation mode supports a multiply accumulate operation of a floating-point number of a first bit width k. The method further includes dividing fractional parts of first and second operands into m first and second suboperands of a second bit width k. The second bit width k=k/m. The method further includes performing a multiplication operation based on the m first and second suboperands to obtain a fractional product, and determining a floating-point number sum based on the fractional product and a third operand.