Avoiding commanded system-on-chip (soc) sleep entry failure in processor-based devices

Abstract

Avoiding commanded System-on-Chip (SoC) sleep entry failure in processor-based devices is disclosed herein. In some aspects, a processor-based device comprises a low-power mode (LPM) compliance logic circuit that receives, from each of a plurality of subsystem circuits, a corresponding indication to start a corresponding No Acknowledgement (NACK) timer of a plurality of NACK timers. The LPM compliance logic circuit generates a plurality of NACK timer status indications corresponding to the plurality of NACK timers, wherein each NACK timer status indication is set to a first value if the corresponding NACK timer is cancelled by the corresponding subsystem circuit upon entry into an LPM, or is set to a second value if the corresponding NACK timer expires without being cancelled. The LPM compliance logic circuit generates an LPM compliance status indication in response to the NACK timer status indications and an enable indication.