Interconnect process monitor for assessing wire parasitics across configurations

Abstract

Disclosed embodiments provide methods, systems, and computer program products for process monitoring of interconnect wiring configurations and determining interconnect wiring characteristics including resistor-capacitator (RC) delay and capacitance parasitics of a given interconnect wiring configuration of a chip design. A disclosed interconnect monitor structure includes multiple stages, where each stage includes a source latch to receive scan test pattern input, a buffered wire segment including defined interconnect wire and threshold voltage configurations, and a capture latch capturing output test scan patterns. Disclosed test pattern generation implementations enable efficient and effective wiring interconnect process monitoring and identifying interconnect wiring characteristics and performance for an interconnect wiring configuration of a given IC design.