The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Oct. 30, 2024
Applicant:

Intelligent Memory Limited, Kwai Chung, HK;

Inventor:

Peter Poechmueller, Jinan, CN;

Assignee:

Intelligent Memory Limited, Kwai Chung, HK;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 1/073 (2006.01); G01R 1/067 (2006.01);
U.S. Cl.
CPC ...
G01R 1/07342 (2013.01); G01R 1/0675 (2013.01);
Abstract

A motherboard assembly for testing wafers is described. The motherboard assembly includes a probe card having a plurality of needles disposed in a center region and a plurality of micro connectors disposed outside the center region. Each micro connector is communicatively coupled with a plurality of needles. The motherboard assembly also includes a lower motherboard comprising a plurality of tiles, each tile having at least one processor and at least one memory channel. Each memory channel is communicatively coupled with a micro connector of the probe card. A gap vertically separates and insulates the lower motherboard from the probe card. A wafer is sized and dimensioned to rest on the needles of the probe card for testing.


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Poechmueller, Peter. (2026). Multiple tile wafer tester (U.S. Patent No. 12782394). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12782394

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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