The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2026

Filed:

Mar. 13, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seulki Hong, Suwon-si, KR;

Younghan Kim, Suwon-si, KR;

Jaeyeop Lee, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10W 20/00 (2026.01); H10W 20/41 (2026.01); H10W 20/43 (2026.01); H10D 30/69 (2025.01); H10D 84/01 (2025.01);
U.S. Cl.
CPC ...
H10W 20/435 (2026.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01); H10D 64/256 (2025.01); H10D 64/258 (2025.01); H10W 20/082 (2026.01); H10W 20/089 (2026.01); H10W 20/43 (2026.01); H10D 30/62 (2025.01); H10D 30/797 (2025.01); H10D 64/0112 (2026.01); H10D 84/0158 (2025.01); H10W 20/076 (2026.01);
Abstract

A semiconductor device includes a first gate structure, a first source/drain layer and a first contact plug. The first gate structure is formed on a substrate, and extends in a second direction parallel to an upper surface of the substrate. The first source/drain layer is formed at a side of the first gate structure in a first direction substantially parallel to the upper surface of the substrate and crossing the second direction. A central portion in the first direction of an upper surface of the first source/drain layer is lower than an edge portion in the first direction of the upper surface of the first source/drain layer. The first contact plug is formed on the first source/drain layer, and contacts the edge portion of the upper surface of the first source/drain layer.


Find Patent Forward Citations

Quick Actions:

Hong, Seulki. (2026). Semiconductor device having a contact interface offset from a lowermost point of a source/drain upper surface (U.S. Patent No. 12777914). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12777914

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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