The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2026

Filed:

Dec. 14, 2021
Applicants:

Beijing Superstring Academy of Memory Technology, Beijing, CN;

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Huilong Zhu, Poughkeepsie, NY (US);

Zhongrui Xiao, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/66 (2025.01); H10D 30/01 (2025.01); H10D 62/17 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10P 52/40 (2026.01); H10P 76/20 (2026.01);
U.S. Cl.
CPC ...
H10D 30/66 (2025.01); H10D 30/0291 (2025.01); H10D 62/235 (2025.01); H10D 64/017 (2025.01); H10D 64/512 (2025.01); H10P 52/402 (2026.01); H10P 76/2041 (2026.01);
Abstract

The vertical MOSFET device includes: an active region including a first source/drain layer, a channel layer and a second source/drain layer vertically stacked on a substrate in sequence, wherein an outer periphery of the channel layer is recessed with respect to outer peripheries of the first source/drain layer and the second source/drain layer; a spacing layer including an upper spacing layer and a lower spacing layer, wherein the upper spacing layer and the lower spacing layer are both in contact with a side surface of the channel layer and are not in communication with each other; and a gate stack formed at least on a lateral outer periphery of the channel layer and embedded in a groove space between the upper spacing layer and the lower spacing layer.


Find Patent Forward Citations

Zhu, Huilong. (2026). Vertical mosfet device and method of manufacturing vertical mosfet device (U.S. Patent No. 12777674). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12777674

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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