Jitter correction in a receiver device

Abstract

Technologies for jitter extraction are described. A receiver device includes an analog-to-digital converter (ADC) and a signal processing circuit. The signal processing circuit includes an equalizer block, a phase detector block, and a jitter correction block. The jitter correction block can receive current data from the equalizer block, determine a running sum value based on phase information received from the phase detector block, apply either a first gain value or a second gain value to the running sum value to obtain a phase correction value based on a sign of the running sum value, wherein the first gain value and the second gain value are different, and re-sample, using the phase correction value, the current data to obtain re-sampled data to reduce jitter in the current data.