The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2026

Filed:

Dec. 22, 2022
Applicant:

Intel Products Ip Llc, Santa Clara, CA (US);

Inventors:

Zeev Toroker, Haifa, IL;

Daljeet Kumar, New Delhi, IN;

Yevgeny Perelman, Haifa, IL;

Assignee:

Intel Products IP LLC, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); H03K 3/017 (2006.01); H03K 5/05 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 3/017 (2013.01); H03K 5/05 (2013.01); H03K 2005/00026 (2013.01);
Abstract

Some embodiments include apparatuses comprising a first node; a second node; a first transistor and a second transistor, the first and second transistors including a common gate coupled to the node and a common terminal coupled to the second node; first additional transistors coupled in parallel with each other between a terminal of the first transistor and a first supply node, the first additional transistors including gates; and second additional transistors coupled in parallel with each other between a terminal of the second transistor and a second supply node, the second additional transistors including gates.


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Toroker, Zeev. (2026). Clock adjustment circuit with bias scheme (U.S. Patent No. 12776761). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12776761

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