The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2026

Filed:

Dec. 20, 2022
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Terence Magee, San Francisco, CA (US);

Jeffrey Schulz, Milpitas, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G11C 7/1066 (2013.01); G11C 7/1069 (2013.01);
Abstract

Systems or methods may provide a programmable logic fabric and a memory controller communicatively coupled to the programmable logic fabric. The systems or methods also include a physical layer and IO circuit coupled to the programmable logic fabric via the memory controller and a FIFO to receive read data from a memory device coupled to the physical layer and IO circuit. Furthermore, the FIFO is closer to the memory controller than to the physical layer and IO circuit.


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Magee, Terence. (2026). Source synchronous partition of an sdram controller subsystem (U.S. Patent No. 12776354). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12776354

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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