Semiconductor memory device having staircase conductive region

Abstract

According to one embodiment, a semiconductor memory device has a first region with first conductive layers stacked in a first direction and first columnar portions, a second region with second conductive layers stacked in the first direction and second columnar portions extending in the first direction through the second conductive layers, and a third region between the first and second regions in a second direction and including third conductive layers between the first conductive layers and the second conductive layers in the second direction. A plurality of switches are arranged along the second direction to be below the first, second, and third regions. First contacts are provided to electrically connect the third conductive layers to the switches. The third conductive layers are in a staircase shape that gets nearest to the switches in a middle portion and recedes toward end portions.