The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2026

Filed:

Sep. 06, 2023
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Sandip Maity, Bangalore, IN;

Chun Zhang, San Jose, CA (US);

Aman Gayasen, Hyderabad, IN;

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 111/10 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 2111/10 (2020.01);
Abstract

Control set optimization for a circuit design includes generating, by a processor, Observability Don't Care (ODC) expressions for registers of the circuit design. Redundant reset pins of the registers of the circuit design are determined by the processor by iteratively checking, on a per-cube and a per-literal basis for each ODC expression, whether a value of a literal causes the ODC expression to evaluate to 1. A modified version of the circuit design is generated by the processor by connecting one or more reset pins of the set of redundant reset pins to one or more constants.


Find Patent Forward Citations

Maity, Sandip. (2026). Control set optimization for circuit designs by detection of registers with redundant resets (U.S. Patent No. 12775775). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12775775

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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