The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2026

Filed:

May. 11, 2023
Applicant:

Mediatek Inc., Hsinchu City, TW;

Inventors:

Jen-Wei Lee, Hsinchu City, TW;

Yi-Ying Liao, Hsinchu City, TW;

Te-Wei Chen, Hsinchu City, TW;

Yu-Hsiu Lin, Hsinchu City, TW;

Chia-Wei Chen, Hsinchu City, TW;

Chun-Ku Ting, Hsinchu City, TW;

Sheng-Tai Tseng, Hsinchu City, TW;

Ronald Kuo-Hua Ho, Hsinchu City, TW;

Hsin-Chuan Kuo, Hsinchu City, TW;

Chun-Chieh Wang, Hsinchu City, TW;

Ming-Fang Tsai, Hsinchu City, TW;

Chun-Chih Yang, Hsinchu City, TW;

Tai-Lai Tung, Hsinchu City, TW;

Da-Shan Shiu, Hsinchu City, TW;

Assignee:

MediaTek Inc., Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/392 (2020.01); G06F 111/20 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/392 (2020.01); G06F 2111/20 (2020.01);
Abstract

A neural network based method places flexible blocks on a chip canvas in an integrated circuit (IC) design. The neural network receives an input describing geometric features of a flexible block to be placed on the chip canvas. The geometric features includes an area size and multiple aspect ratios. The neural network generates a probability distribution over locations on the chip canvas and the aspect ratios of the flexible block. Based on the probability distribution, a location on the chip canvas is selected for placing the flexible block with a chosen aspect ratio.


Find Patent Forward Citations

Quick Actions:

Lee, Jen-Wei. (2026). Learning-based placement of flexible circuit blocks (U.S. Patent No. 12775774). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12775774

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