Coarse-grained reconfigurable processor array with optimized buffers

Abstract

A system and method for transforming a high-level program into configuration data for a coarse-grained reconfigurable (CGR) data processor with an array of CGR units. The high-level program is transformed into a dataflow graph that includes multiple interdependent asynchronously performing meta-pipelines. A first buffer is identified that stores data that is passed from a producer in a first meta-pipeline stage to a consumer in a second meta-pipeline stage. The system determines limitations associated with the array, and selects for implementation the lowest-cost buffer topology, chosen from a cascaded buffer topology, a hybrid buffer topology, and a striped buffer topology, where cost is determined by the number of memory units and on a number of times data is written into a memory unit while traveling through the first buffer. Optimal configuration data for the array is generated and stored.