The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 2026
Filed:
Oct. 25, 2021
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Hyunchul Hwang, Suwon-si, KR;
Hyun Lee, Yongin-si, KR;
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/501 (2006.01); H03K 19/20 (2006.01); G06F 7/57 (2006.01);
U.S. Cl.
CPC ...
G06F 7/501 (2013.01); H03K 19/20 (2013.01); G06F 7/57 (2013.01);
Abstract
An adder integrated circuit includes a first logic gate group that outputs a first internal signal and a second internal signal based on a first input signal and a second input signal, a second logic gate group that outputs a sum signal based on the second internal signal and a third input signal, and a third logic gate group that outputs a carry signal based on the first internal signal, the second internal signal, and the third input signal.
Quick Actions:
Hwang, Hyunchul. (2026). Full adder integrated circuit and 4-2 compressor integrated circuit based on the full adder integrated circuit (U.S. Patent No. 12775445). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12775445
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile