The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2026

Filed:

Sep. 18, 2023
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Kumar Nagarajan, Cupertino, CA (US);

Flynn P. Carson, Redwood City, CA (US);

Karthik Shanmugam, Singapore, SG;

Seongmin Lee, Yeonsu-Gu, KR;

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/01 (2026.01); H10W 74/121 (2026.01); H10W 90/00 (2026.01); H10W 90/701 (2026.01); H10W 90/724 (2026.01);
Abstract

Electronic packages and methods of formation are described. In an embodiment, an electronic package includes one or more electronic components encapsulated in a step molded molding compound layer, and wiring layer spanning a lower step surface, sidewall, and top surface of the step molded molding compound layer. The wiring layer may further extend into a via opening extending through the lower step surface of the molding compound layer.


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Quick Actions:

Nagarajan, Kumar. (2026). Electronic package molded vertical interconnection (U.S. Patent No. 12772885). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12772885

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