The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2026

Filed:

Sep. 23, 2022
Applicant:

Samsung Display Co., Ltd., Yongin-Si, KR;

Inventors:

Shinhyuk Yang, Yongin-si, KR;

Donghan Kang, Yongin-si, KR;

Yujin Kim, Yongin-si, KR;

Jeehoon Kim, Yongin-si, KR;

Junki Lee, Yongin-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10K 59/131 (2023.01); H10K 59/12 (2023.01); H10K 71/00 (2023.01); H10W 72/00 (2026.01); H10W 72/90 (2026.01);
U.S. Cl.
CPC ...
H10K 59/131 (2023.02); H10K 71/00 (2023.02); H10K 59/1201 (2023.02); H10W 72/01938 (2026.01); H10W 72/01953 (2026.01); H10W 72/01971 (2026.01); H10W 72/90 (2026.01); H10W 72/923 (2026.01); H10W 72/934 (2026.01); H10W 72/9415 (2026.01); H10W 72/942 (2026.01); H10W 72/952 (2026.01); H10W 72/953 (2026.01);
Abstract

A display apparatus is disclosed that includes a substrate, a display element, a transistor, and a pad. The substrate includes a display area and a peripheral area. The display element is disposed on the display area. The transistor is electrically connected to the display element. The pad is disposed on the peripheral area and having a multilayered structure. The pad includes a pad metal layer, a first pad protective layer disposed on the pad metal layer, and a second pad protective layer interposed between the pad metal layer and the first pad protective layer. The second pad protective layer includes a different material from the first pad protective layer. The transistor includes a semiconductor layer disposed on the substrate, a gate electrode disposed on a gate insulating layer that covers the semiconductor layer, and a connection electrode arranged on an interlayer insulating layer covering the gate electrode. The connection electrode has the same multilayered structure as the multilayered structure of the pad, and the connection electrode is connected to the semiconductor layer.


Find Patent Forward Citations

Yang, Shinhyuk. (2026). Display apparatus having a pad protective layer disposed on a pad metal layer (U.S. Patent No. 12772678). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12772678

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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