Method for fabricating vertical channel nanowire transistor with asymmetric stress distribution

Abstract

A method for fabricating a vertical channel nanowire transistor with asymmetric stress distribution includes: (A) growing epitaxially a single-crystal material on a substrate; forming a laminate of a bottom source-drain material and a channel material; and generating a vertical uniaxial stress in the lightly-doped channel layer; (B) forming an inter-device isolation in an active layer; (C) forming a vertical channel by patterning; (D) depositing a dielectric layer to form a bottom gate isolation; (E) depositing a dummy gate layer followed by patterning to form a dummy gate pattern; (F) depositing a dielectric layer to form a top gate isolation; (G) patterning the top gate isolation; and forming a top source-drain by epitaxy growth; (H) removing a dummy gate; and forming a gate oxide layer and a metal gate; and (I) forming metal contact at individual ends of the device.