The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2026

Filed:

Aug. 31, 2023
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Tomohiro Kubo, Yokkaichi, JP;

Takayuki Maekura, Yokkaichi, JP;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); G11C 16/04 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10W 20/41 (2026.01); H10W 20/42 (2026.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); G11C 16/0483 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10W 20/42 (2026.01); H10W 20/435 (2026.01);
Abstract

A method includes forming an in-process alternating stack of insulating layers and sacrificial material layers, forming a meandering dielectric isolation structure through the in-process alternating stack, forming memory stack structures through the alternating stack, where each of the memory stack structures includes a respective vertical stack of memory elements and a vertical semiconductor channel, forming sacrificial via fill structures on the respective sacrificial material layers, replacing first portions of the sacrificial material layers with electrically conductive layers, and forming layer contact via structures contacting a respective one of the electrically conductive layers by replacing at least the sacrificial via fill structures with a conductive material portion.


Find Patent Forward Citations

Kubo, Tomohiro. (2026). Stairless three-dimensional memory device containing meandering dielectric isolation structure and methods of forming the same (U.S. Patent No. 12772448). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12772448

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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