Continuous-time pipeline adc and method for calibrating a digital filter of a continuous-time pipeline adc

Abstract

A continuous-time analog-to-digital converter circuit includes an input configured to receive an analog input signal; a delay element with a specified time delay, the delay element functionally connected between the input and a first summation node; a ADC-DAC path with a sub ADC and a sub DAC connected between the input and the first summation node. The ADC-DAC path is configured to digitize the analog input signal and to reconvert the digitized signal to analog domain and to subtract it at the first summation node. An output of the first summation node is filtered by means of a continuous-time filter and an output of the continuous-time filter is clocked by a specified sampling rate. A backend ADC is configured to digitize the clocked output of the analog filter and to connect the clocked output to a second summation node. An output is obtained by a summation of the output of the backend ADC and an output of a digital filter is connected to the sub ADC. The digital filter is configured to represent a replica of a transfer function of the sampled output of the continuous-time filter in the digital domain.