The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2026

Filed:

Dec. 19, 2024
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Vivekanandan Venugopal, Saratoga, CA (US);

Ajay Bhatia, Saratoga, CA (US);

Animesh Datta, San Diego, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0185 (2006.01); H03L 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018521 (2013.01);
Abstract

Glitch suppression in a level shifting circuit during power up is disclosed. A level shifting circuit is configured to receive an input signal based on a first voltage domain and generate an output signal based on a second voltage domain. The level shifting circuit is also configured to receive a control signal that is operable to suppress the output signal. A control circuit is configured to provide the control signal to the level shifting circuit such that the output signal fluctuations of the level shifting circuit is suppressed during a power up to a power supply voltage.


Find Patent Forward Citations

Venugopal, Vivekanandan. (2026). Glitch suppression in a level shifting circuit during power up (U.S. Patent No. 12771349). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12771349

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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