Fast-settling delay line assisted by replica delay line

Abstract

A fast-settling delay line having a reduced or negligible delay variation in response to enabling the delay line includes a replica load coupled to a control node of a main delay line before a first edge of a clock input to the main delay line. The replica load is equivalent to the load on the control node introduced by the main delay line in response to the first edge of the clock input to the main delay line. In an embodiment, the replica delay line receives a replica clock signal that has the same frequency as the clock input to the main delay line. After a few cycles of the replica clock signal, the control voltage is stable and control logic switches off the replica delay line and turns on the main delay line.