Link stress pattern to ensure command address bus integrity

Abstract

Embodiments herein describe link stress patterns to ensure command address bus integrity. In an example, a memory controller asserts a link stress pattern of bits on command address (CA) links of a CA bus of a dynamic random-access memory (DRAM) device, while the DRAM device is in a pre-operating state in which the DRAM device does not recognize memory access commands and in which a CA bus parity circuit of the DRAM device is enabled, where the link stress pattern of bits extends over multiple clock cycles of the DRAM device. The memory controller also monitors an error output of the DRAM device for parity errors, while asserting the link stress pattern of bits on the CA links.