Shift register, gate driving circuit and display panel

Abstract

A shift register includes a first input sub-circuit configured to cause a first power supply voltage to be written into a first node, a second input sub-circuit configured to cause a signal of the first-type clock signal end to be written into the first node, a first output unit configured to cause a second power supply voltage to be written into a signal output end, a first control sub-circuit configured to cause a signal of a second-type clock signal end to be written into a second node, a second control sub-circuit configured to cause the signal of the second-type clock signal end to be written into a third node, a third control sub-circuit configured to cause conduction between the third node and the second node, and a second output unit configured to cause the first power supply voltage to be written into the signal output end.