The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2026
Filed:
Sep. 11, 2023
Faraday Technology Corporation, Hsinchu City, TW;
Chin-Cheng Chen, Hsinchu City, TW;
Jui-Hung Hung, Hsinchu City, TW;
Jen-Hsing Lin, Hsinchu City, TW;
FARADAY TECHNOLOGY CORPORATION, Hsinchu City, TW;
Abstract
A layout method, a non-transitory computer-readable medium, and an associated integrated circuit are provided. The non-transitory computer-readable medium records a software program for performing the layout method of the integrated circuit having Q circuit blocks. The layout method includes the following steps. K gate-controlled elements and (K−1) buffers are placed on the edge of a qth circuit block. The K gate-controlled elements are connected between a supply voltage terminal and the qth circuit block. (K−1) gate-controlled elements, including an SEL[1]-th gate-controlled element, are selected as (K−1) source nodes. Another (K−1) gate-controlled elements, other than the SEL[1]-th gate-controlled element, are selected as (K−1) destination nodes. The (K−1) buffers are routed as (K−1) delayed gating lines connected between the (K−1) source nodes and the (K−1) destination nodes.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile