logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12769805 B1

PDFFull Text
Date of Patent:
Oct. 20, 2026

Filed:

Oct. 04, 2021

Matrix multiply accelerator for variable bitwidth operands

Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Zhi-Gang Liu, Westford, MA (US);

Paul Nicholas Whatmough, Cambridge, MA (US);

Matthew Mattina, Boylston, MA (US);

John Fremont Brown, III, Marion, MA (US);

Assignee:

Arm Limited, Cambridge, GB;

Attorney:

Leveque Intellectual Property Law, P.C.

Primary Examiner:

Andrew Caldwell

Assistant Examiner:

Kenny K. Bui

Int. Cl.
CPC ...
G06F 17/16 (2006.01); G06F 5/01 (2006.01); G06F 7/501 (2006.01); G06F 7/523 (2006.01); G06F 7/544 (2006.01); G06F 9/50 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G06F 17/16 (2013.01); G06F 5/01 (2013.01); G06F 7/501 (2013.01); G06F 7/523 (2013.01); G06F 7/5443 (2013.01); G06F 9/5027 (2013.01); H03K 19/20 (2013.01);
Abstract

A system and method for multiplying first and second matrices are provided. For the first matrix, a number of bit slice vectors for each row are generated based on the bit resolution, and a first bit slice tensor is generated based on the bit slice vectors for each row. For the second matrix, a number of bit slice vectors for each column are generated based on the bit resolution, and a second bit slice tensor is generated based on the bit slice vectors for each row. The first and second bit slice tensors are multiplied by a matrix multiply accelerator (MMA) to generate an output matrix.

Find Patent Forward Citations

Liu, Zhi-Gang. (2026). Matrix multiply accelerator for variable bitwidth operands (U.S. Patent No. 12769805). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12769805

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…