Preamble data alignment for constant latency

Abstract

Aspects of a data sink for aligning data between a source and a sink are described herein. An example data sink includes timing circuitry configured to generate an output clock signal, the output clock signal having a variable phase based at least in part on receipt of a reference clock signal, and where the reference clock signal is transmitted from a source. The data sink further includes a verification module configured to receive a data synchronization pattern, the received data synchronization pattern including a sequence of bits that is positionally shifted based at least in part on the variable phase. The verification module is further configured to determine a shift quantity to be removed from incoming data for training a first data bus, the shift quantity determined based on the sequence of bits that is positionally shifted.