The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2026

Filed:

Jul. 31, 2024
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Ravi Pratap Singh, Austin, TX (US);

Sreenivas Krishnan, Campbell, CA (US);

Ching-Yu Hung, Pleasanton, CA (US);

Jagadeesh Sankaran, Dublin, CA (US);

Yen-Te Shih, Zhubei City, TW;

Andrew Peter Taussig, Scottsdale, AZ (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 13/1689 (2013.01); G06F 9/30043 (2013.01); G06F 13/1673 (2013.01);
Abstract

Aspects of this technical solution can provide at least a technical improvement to reading and writing data between a memory device and a processor, including, for example, by providing a technical solution to configure one or more load streams with stream sizes configured based on relative speed of a processor and a memory. For example, this technical solution can provide a technical improvement to processing speed of computations by a processor with data obtained from or stored to a memory device. For example, a system in accordance with this technical solution can provide a decoupled load store unit (DLSU) distinct from a processor and a memory device to prefetch a sufficient amount of data from a memory device into a stream buffer of a DLSU, to provide instructions to a processor at a rate that eliminates waiting by the processor for memory over one or more cycles.


Find Patent Forward Citations

Singh, Ravi. (2026). Memory architecture (U.S. Patent No. 12769677). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12769677

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…