Computing device with cache memory optimized for matrix computing

Abstract

The present description concerns a computing device comprising a computing unit; a main memory; a cache memory configured to exchange data with the computing unit and the main memory, and comprising a circuit for calculating reduction operations between partial products derived from values of a sparse matrix and an input vector, and an output vector, wherein the cache memory comprises a first N-way set associative memory region storing, with a first word granularity T, values of results of reduction operations performed by the computing circuit based on partial products derived from values of a dense region of the matrix, and a second fully associative or M-way set associative memory region storing, with a second word granularity T, values of results of reduction operations performed by the computing circuit based on partial products derived from values of a sparse region of the matrix, with M≥N, T≥T, and also M>N if T=Tand T>Tif M=N.