Artificial neural network processing accelerator based on systolic array and method for data rearrangement therein

Abstract

Disclosed herein is an artificial neural network processing accelerator based on a systolic array. The artificial neural network processing accelerator based on a systolic array includes a processing element array, internal memory for storing input/output data of the processing element array, and a data flow control unit for performing control to deliver an input tensor and weight data from the internal memory to the processing element array in each operation cycle and to store an output tensor from the processing element array in the internal memory. The internal memory may include N memory banks respectively corresponding to N rows of the processing element array and further include a rearrangement interface for connecting input/output between the N rows of the processing element array and the N memory banks.