Providing adaptive and dynamic redundancy for functional safety in processor devices

Abstract

Providing adaptive and dynamic redundancy for functional safety in processor devices is disclosed herein. In some aspects, a processor device comprises a central configurable redundancy logic block (CRLB) controller circuit, a redundancy map matrix switch circuit, a plurality of safety-critical block circuits, and a plurality of CRLB clusters. The central CRLB controller circuit receives redundancy mapping data for each safety-critical block circuit, and receives an indication of one or more active block circuits among the safety-critical block circuits. The central CRLB controller circuit transmits the redundancy mapping data corresponding to the active block circuits to the redundancy map matrix switch circuit, which configures one or more CRLB clusters to duplicate functionality of the respective active block circuits based on the redundancy mapping data. The redundancy map matrix switch circuit then provides logic redundancy for the one or more active block circuits using the one or more CRLB clusters.