Synchronization of predetermined class of load/store operations

Abstract

For a predetermined class of load/store operations, load/store processing circuitry buffers store data of predetermined-class store operations in a predetermined-class store buffer, and controls store-to-load forwarding of store data from that buffer to predetermined-class load operations. A predetermined-class-load/store synchronization instruction controls the load/store processing circuitry to enforce that, for a hazarding younger non-predetermined-class load/store operation occurring after the predetermined-class-load/store synchronization instruction in program order and a hazarding older predetermined-class store operation occurring before the predetermined-class-load/store synchronization instruction in program order, for which address ranges overlap, the hazarding younger non-predetermined-class load/store operation observes a result of the hazarding older predetermined-class store operation. In absence of any intervening predetermined-class-load/store synchronization instruction between a given older predetermined-class store operation and a given younger non-predetermined-class load/store operation with overlapping address range, the given younger non-predetermined-class load/store operation is permitted to fail to observe a result of the given older predetermined-class store operation.