The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2026

Filed:

Apr. 23, 2024
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Chih-Chieh Chang, Hsinchu City, TW;

You-Hong Sun, Hsinchu City, TW;

Wen-Hsun Lin, Hsinchu City, TW;

Chia-Ching Chang, Hsinchu City, TW;

Assignee:

MEDIATEK INC., Hsinchu City, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0625 (2013.01); G06F 3/0653 (2013.01); G06F 3/0673 (2013.01);
Abstract

A memory access latency estimation method includes measuring a first access latency of a first access operation of a first memory, measuring a plurality of first indexes of the first memory corresponding to the first access operation, using a plurality of first coefficients and the plurality of first indexes to perform a first weighted calculation to generate a first estimated latency, adjusting the plurality of first coefficients to generate a plurality of updated first coefficients, using the plurality of updated first coefficients and the plurality of first indexes to perform the first weighted calculation to adjust the first estimated latency for the first estimated latency to approximate the first access latency, and using the plurality of updated first coefficients and a plurality of second indexes of the first memory to perform a second weighted calculation to generate a second estimated latency for a second access operation.


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Chang, Chih-Chieh. (2026). Memory access latency estimation method and memory access latency estimation system for estimating an access latency of a memory according to a plurality of coefficients and a plurality of indexes (U.S. Patent No. 12769464). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12769464

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