Enhanced deep sleep operations for systems with homogeneous chip architectures

Abstract

This disclosure provides systems, methods, and devices for memory systems that support enhanced processing core scheduling schemes. In a first aspect, a system-on-a-chip (SoC) includes at least one processor, and a memory coupled to the at least one processor. The at least one processor is configured to cause the SoC to: initiate, by an application processor subsystem (APSS) of the SoC, deep sleep mode entry based on determining a deep sleep entry trigger has been satisfied; coordinate, between a primary chiplet and a secondary chiplet of the SoC, to collapse subsystems of the primary and secondary chiplets and to put double data rate (DDR) memory of the SoC into a self-refresh mode; trigger, by the primary chiplet, programable boot sequence (PBS) operations of a primary power management integrated controller (PMIC) of the primary chiplet; and collapse, by the primary PMIC, SoC power rails. Other aspects and features are also claimed and described.